In order to form integrated circuits on wafers, lithography process is used. A typical lithography process involves applying a photo resist, and defining patterns on the photo resist. The patterns in the patterned photo resist are defined in a lithography mask, and are defined either by the transparent portions or by the opaque portions in the lithography mask. The patterns in the patterned photo resist are then transferred to the underlying features through an etching step, wherein the patterned photo resist is used as an etching mask. After the etching step, the patterned photo resist is removed.
With the increasing down-scaling of integrated circuits, optical proximity effect posts an increasingly greater problem for transferring patterns from lithography mask to wafers. When two separate features are too close to each other, the optical proximity effect may cause the resulting formed features too short to each other. To solve such a problem, double-patterning technology was introduced for enhancing feature density without incurring optical proximity effect. One of the double patterning technologies uses two-patterning-two-etching (2P2E). The closely located features are separated into two lithography masks, with both lithography masks used to expose the same photo resist or two photo resists, so that the closed located patterns may be transferred to a same layer such as a low-k dielectric layer. In each of the double patterning lithography masks, the distances between the features are increased over the distances between the features in the otherwise single patterning mask, and may be practically doubled when necessary. The distances in the double patterning lithography masks are greater than the threshold distances of the optical proximity effect, and hence the optical proximity effect is at least reduced, or substantially eliminated.